Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Hisilicon Hi3798CV200 specific extensions to the Synopsys Designware Mobile
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)   Storage Host Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Read synopsys-dw-mshc.txt for more details
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) The Synopsys designware mobile storage host controller is used to interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) differences between the core Synopsys dw mshc controller properties described
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) by synopsys-dw-mshc.txt and the properties used by the Hisilicon Hi3798CV200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) specific extensions to the Synopsys Designware Mobile Storage Host Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - compatible: Should contain "hisilicon,hi3798cv200-dw-mshc".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - clocks: A list of phandle + clock-specifier pairs for the clocks listed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   in clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - clock-names: Should contain the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	"ciu" - The ciu clock described in synopsys-dw-mshc.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	"biu" - The biu clock described in synopsys-dw-mshc.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	"ciu-sample" - Hi3798CV200 extended phase clock for ciu sampling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	"ciu-drive"  - Hi3798CV200 extended phase clock for ciu driving.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	emmc: mmc@9830000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		compatible = "hisilicon,hi3798cv200-dw-mshc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		reg = <0x9830000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		clocks = <&crg HISTB_MMC_CIU_CLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 			 <&crg HISTB_MMC_BIU_CLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 			 <&crg HISTB_MMC_SAMPLE_CLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 			 <&crg HISTB_MMC_DRV_CLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		fifo-depth = <256>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		clock-frequency = <200000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		cap-mmc-highspeed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		mmc-ddr-1_8v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		mmc-hs200-1_8v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		non-removable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		bus-width = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	};