^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) $id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - Shawn Guo <shawnguo@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) allOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - $ref: "mmc-controller.yaml"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) The Enhanced Secure Digital Host Controller on Freescale i.MX family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) provides an interface for MMC, SD, and SDIO types of memory cards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) This file documents differences between the core properties described
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) oneOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - fsl,imx25-esdhc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - fsl,imx35-esdhc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - fsl,imx51-esdhc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - fsl,imx53-esdhc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - fsl,imx6q-usdhc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - fsl,imx6sl-usdhc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - fsl,imx6sx-usdhc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - fsl,imx6ull-usdhc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - fsl,imx7d-usdhc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - fsl,imx7ulp-usdhc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - fsl,imx8mm-usdhc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - fsl,imx8mn-usdhc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - fsl,imx8mp-usdhc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - fsl,imx8mq-usdhc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - fsl,imx8qxp-usdhc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - const: fsl,imx7d-usdhc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) fsl,wp-controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) boolean, if present, indicate to use controller internal write protection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) fsl,delay-line:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) Specify the number of delay cells for override mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) This is used to set the clock delay for DLL(Delay Line) on override mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) to select a proper data sampling window in case the clock quality is not good
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) due to signal path is too long on the board. Please refer to eSDHC/uSDHC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) chapter, DLL (Delay Line) section in RM for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) default: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) voltage-ranges:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) $ref: '/schemas/types.yaml#/definitions/uint32-matrix'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) Specify the voltage range in case there are software transparent level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) shifters on the outputs of the controller. Two cells are required, first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) cell specifies minimum slot voltage (mV), second cell specifies maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) slot voltage (mV).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) - description: value for minimum slot voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) - description: value for maximum slot voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) fsl,tuning-start-tap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) Specify the start delay cell point when send first CMD19 in tuning procedure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) default: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) fsl,tuning-step:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) Specify the increasing delay cell steps in tuning procedure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) The uSDHC use one delay cell as default increasing step to do tuning process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) This property allows user to change the tuning step to more than one delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) cells which is useful for some special boards or cards when the default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) tuning step can't find the proper delay window within limited tuning retries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) default: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) fsl,strobe-dll-delay-target:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) Specify the strobe dll control slave delay target.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) This delay target programming host controller loopback read clock, and this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) property allows user to change the delay target for the strobe input read clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) If not use this property, driver default set the delay target to value 7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) Only eMMC HS400 mode need to take care of this property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) default: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) - interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unevaluatedProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) mmc@70004000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) compatible = "fsl,imx51-esdhc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) reg = <0x70004000 0x4000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) interrupts = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) fsl,wp-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) mmc@70008000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) compatible = "fsl,imx51-esdhc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) reg = <0x70008000 0x4000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) interrupts = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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