^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Freescale Enhanced Secure Digital Host Controller (eSDHC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) The Enhanced Secure Digital Host Controller provides an interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) for MMC, SD, and SDIO types of memory cards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) This file documents differences between the core properties described
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) by mmc.txt and the properties used by the sdhci-esdhc driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - compatible : should be "fsl,esdhc", or "fsl,<chip>-esdhc".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Possible compatibles for PowerPC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) "fsl,mpc8536-esdhc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) "fsl,mpc8378-esdhc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) "fsl,p2020-esdhc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) "fsl,p4080-esdhc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) "fsl,t1040-esdhc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) "fsl,t4240-esdhc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Possible compatibles for ARM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) "fsl,ls1012a-esdhc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) "fsl,ls1028a-esdhc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) "fsl,ls1088a-esdhc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) "fsl,ls1043a-esdhc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) "fsl,ls1046a-esdhc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) "fsl,ls2080a-esdhc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - clock-frequency : specifies eSDHC base clock frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - sdhci,wp-inverted : specifies that eSDHC controller reports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) inverted write-protect state; New devices should use the generic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) "wp-inverted" property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - sdhci,1-bit-only : specifies that a controller can only handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 1-bit data transfers. New devices should use the generic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) "bus-width = <1>" property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - sdhci,auto-cmd12: specifies that a controller can only handle auto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) CMD12.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - voltage-ranges : two cells are required, first cell specifies minimum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) slot voltage (mV), second cell specifies maximum slot voltage (mV).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) Several ranges could be specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - little-endian : If the host controller is little-endian mode, specify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) this property. The default endian mode is big-endian.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) sdhci@2e000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) reg = <0x2e000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) interrupts = <42 0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) interrupt-parent = <&ipic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Filled in by U-Boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) clock-frequency = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) voltage-ranges = <3300 3300>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };