^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Samsung Exynos specific extensions to the Synopsys Designware Mobile
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) Storage Host Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) The Synopsys designware mobile storage host controller is used to interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) differences between the core Synopsys dw mshc controller properties described
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) extensions to the Synopsys Designware Mobile Storage Host Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * compatible: should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) specific extensions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) specific extensions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) specific extensions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) specific extensions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) specific extensions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) specific extensions having an SMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) in transmit mode and CIU clock phase shift value in receive mode for single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) data rate mode operation. Refer notes below for the order of the cells and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) valid values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) in transmit mode and CIU clock phase shift value in receive mode for double
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) data rate mode operation. Refer notes below for the order of the cells and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) valid values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) shift value for hs400 mode operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) Notes for the sdr-timing and ddr-timing values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) The order of the cells should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - First Cell: CIU clock phase shift value for tx mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) - Second Cell: CIU clock phase shift value for rx mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) Valid values for SDR and DDR CIU clock timing for Exynos5250:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) - valid value for tx phase shift and rx phase shift is 0 to 7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) - when CIU clock divider value is set to 3, all possible 8 phase shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) values can be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) phase shift clocks should be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * samsung,read-strobe-delay: RCLK (Data strobe) delay to control HS400 mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) (Latency value for delay line in Read path)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) Required properties for a slot (Deprecated - Recommend to use one slot per host):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * gpios: specifies a list of gpios used for command, clock and data bus. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) first gpio is the command line and the second gpio is the clock line. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) rest of the gpios (depending on the bus-width property) are the data lines in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) no particular order. The format of the gpio specifier depends on the gpio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) (Deprecated - Refer to Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) The MSHC controller node can be split into two portions, SoC specific and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) board specific portions as listed below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) dwmmc0@12200000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) compatible = "samsung,exynos5250-dw-mshc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) reg = <0x12200000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) interrupts = <0 75 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) dwmmc0@12200000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) cap-mmc-highspeed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) cap-sd-highspeed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) broken-cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) fifo-depth = <0x80>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) card-detect-delay = <200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) samsung,dw-mshc-ciu-div = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) samsung,dw-mshc-sdr-timing = <2 3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) samsung,dw-mshc-ddr-timing = <1 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) samsung,dw-mshc-hs400-timing = <0 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) samsung,read-strobe-delay = <90>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) bus-width = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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