Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * QEMU PVPANIC MMIO Configuration bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) QEMU's emulation / virtualization targets provide the following PVPANIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) MMIO Configuration interface on the "virt" machine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) type:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - a read-write, 16-bit wide data register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) QEMU exposes the data register to guests as memory mapped registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - compatible: "qemu,pvpanic-mmio".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - reg: the MMIO region used by the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   * Bytes 0x0  Write panic event to the reg when guest OS panics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   * Bytes 0x1  Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)         #size-cells = <0x2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)         #address-cells = <0x2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)         pvpanic-mmio@9060000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)                 compatible = "qemu,pvpanic-mmio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)                 reg = <0x0 0x9060000 0x0 0x2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)         };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)