Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Microsemi MIPS CPUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Boards with a SoC of the Microsemi MIPS family shall have the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - compatible: "mscc,ocelot"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Other peripherals:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) o CPU chip regs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) functionalities: chip ID, general purpose register for software use, reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) controller, hardware status and configuration, efuses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - reg : Should contain registers location and length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	syscon@71070000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		reg = <0x71070000 0x1c>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) o CPU system control:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) endianness, CPU bus control, CPU status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - compatible: Should be "mscc,ocelot-cpu-syscon", "syscon"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - reg : Should contain registers location and length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	syscon@70000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		compatible = "mscc,ocelot-cpu-syscon", "syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		reg = <0x70000000 0x2c>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) o HSIO regs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) The SoC has a few registers (HSIO) handling miscellaneous functionalities:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) configuration and status of PLL5, RCOMP, SyncE, SerDes configurations and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) status, SerDes muxing and a thermal sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) - compatible: Should be "mscc,ocelot-hsio", "syscon", "simple-mfd"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) - reg : Should contain registers location and length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	syscon@10d0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		reg = <0x10d0000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	};