^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) OMAP HS USB Host TLL (Transceiver-Less Interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - compatible : should be "ti,usbhs-tll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - reg : should contain one register range i.e. start and length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - interrupts : should contain the TLL module's interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - ti,hwmod : must contain "usb_tll_hs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - clocks: a list of phandles and clock-specifier pairs, one for each entry in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - clock-names: should include:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * "usb_tll_hs_usb_ch0_clk" - USB TLL channel 0 clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * "usb_tll_hs_usb_ch1_clk" - USB TLL channel 1 clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * "usb_tll_hs_usb_ch2_clk" - USB TLL channel 2 clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) usbhstll: usbhstll@4a062000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) compatible = "ti,usbhs-tll";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) reg = <0x4a062000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) interrupts = <78>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ti,hwmods = "usb_tll_hs";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };