^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) OMAP HS USB Host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - compatible: should be "ti,usbhs-host"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - reg: should contain one register range i.e. start and length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - ti,hwmods: must contain "usb_host_hs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - num-ports: number of USB ports. Usually this is automatically detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) from the IP's revision register but can be overridden by specifying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) this property. A maximum of 3 ports are supported at the moment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - portN-mode: String specifying the port mode for port N, where N can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) from 1 to 3. If the port mode is not specified, that port is treated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) as unused. When specified, it must be one of the following.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) "ehci-phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) "ehci-tll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) "ehci-hsic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) "ohci-phy-6pin-datse0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) "ohci-phy-6pin-dpdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) "ohci-phy-3pin-datse0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) "ohci-phy-4pin-dpdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) "ohci-tll-6pin-datse0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) "ohci-tll-6pin-dpdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) "ohci-tll-3pin-datse0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) "ohci-tll-4pin-dpdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) "ohci-tll-2pin-datse0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) "ohci-tll-2pin-dpdm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - single-ulpi-bypass: Must be present if the controller contains a single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ULPI bypass control bit. e.g. OMAP3 silicon <= ES2.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - clocks: a list of phandles and clock-specifier pairs, one for each entry in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - clock-names: should include:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) For OMAP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * "usbhost_120m_fck" - 120MHz Functional clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) For OMAP4+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * "utmi_p1_gfclk" - Port 1 UTMI clock mux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * "utmi_p2_gfclk" - Port 2 UTMI clock mux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * "usb_host_hs_utmi_p1_clk" - Port 1 UTMI clock gate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * "usb_host_hs_utmi_p2_clk" - Port 2 UTMI clock gate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * "usb_host_hs_utmi_p3_clk" - Port 3 UTMI clock gate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) Required properties if child node exists:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) - #address-cells: Must be 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) - #size-cells: Must be 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) - ranges: must be present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) Properties for children:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) The OMAP HS USB Host subsystem contains EHCI and OHCI controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) See Documentation/devicetree/bindings/usb/ehci-omap.txt and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) Documentation/devicetree/bindings/usb/ohci-omap3.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) Example for OMAP4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) usbhshost: usbhshost@4a064000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) compatible = "ti,usbhs-host";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) reg = <0x4a064000 0x800>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ti,hwmods = "usb_host_hs";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) usbhsohci: ohci@4a064800 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) compatible = "ti,ohci-omap3", "usb-ohci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) reg = <0x4a064800 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) interrupt-parent = <&gic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) interrupts = <0 76 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) usbhsehci: ehci@4a064c00 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) compatible = "ti,ehci-omap", "usb-ehci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) reg = <0x4a064c00 0x400>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) interrupt-parent = <&gic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) interrupts = <0 77 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) &usbhshost {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) port1-mode = "ehci-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) port2-mode = "ehci-tll";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) port3-mode = "ehci-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) &usbhsehci {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) phys = <&hsusb1_phy 0 &hsusb3_phy>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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