Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Freescale MXS LRADC device driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: Should be "fsl,imx23-lradc" for i.MX23 SoC and "fsl,imx28-lradc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)               for i.MX28 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - reg: Address and length of the register set for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - interrupts: Should contain the LRADC interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - fsl,lradc-touchscreen-wires: Number of wires used to connect the touchscreen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)                                to LRADC. Valid value is either 4 or 5. If this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)                                property is not present, then the touchscreen is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)                                disabled. 5 wires is valid for i.MX28 SoC only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - fsl,ave-ctrl: number of samples per direction to calculate an average value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)                 Allowed value is 1 ... 32, default is 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - fsl,ave-delay: delay between consecutive samples. Allowed value is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)                  2 ... 2048. It is used if 'fsl,ave-ctrl' > 1, counts at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)                  2 kHz and its default is 2 (= 1 ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - fsl,settling: delay between plate switch to next sample. Allowed value is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)                 1 ... 2047. It counts at 2 kHz and its default is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)                 10 (= 5 ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Example for i.MX23 SoC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	lradc@80050000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		compatible = "fsl,imx23-lradc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		reg = <0x80050000 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		interrupts = <36 37 38 39 40 41 42 43 44>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		fsl,lradc-touchscreen-wires = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		fsl,ave-ctrl = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		fsl,ave-delay = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		fsl,settling = <10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Example for i.MX28 SoC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	lradc@80050000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		compatible = "fsl,imx28-lradc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		reg = <0x80050000 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		interrupts = <10 14 15 16 17 18 19 20 21 22 23 24 25>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		fsl,lradc-touchscreen-wires = <5>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		fsl,ave-ctrl = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		fsl,ave-delay = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		fsl,settling = <10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	};