^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) MAX77620 Power management IC from Maxim Semiconductor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - compatible: Must be one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) "maxim,max77620"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) "maxim,max20024"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) "maxim,max77663"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - reg: I2C device address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - interrupts: The interrupt on the parent the controller is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) connected to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - interrupt-controller: Marks the device node as an interrupt controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - #interrupt-cells: is <2> and their usage is compliant to the 2 cells
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) variant of <../interrupt-controller/interrupts.txt>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) IRQ numbers for different interrupt source of MAX77620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) are defined at dt-bindings/mfd/max77620.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - system-power-controller: Indicates that this PMIC is controlling the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) system power, see [1] for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) [1] Documentation/devicetree/bindings/power/power-controller.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Optional subnodes and their properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) =======================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Flexible power sequence configurations:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) --------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) The Flexible Power Sequencer (FPS) allows each regulator to power up under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) hardware or software control. Additionally, each regulator can power on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) independently or among a group of other regulators with an adjustable power-up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) and power-down delays (sequencing). GPIO1, GPIO2, and GPIO3 can be programmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) to be part of a sequence allowing external regulators to be sequenced along
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) with internal regulators. 32KHz clock can be programmed to be part of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) The flexible sequencing structure consists of two hardware enable inputs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) (EN0, EN1), and 3 master sequencing timers called FPS0, FPS1 and FPS2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Each master sequencing timer is programmable through its configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) register to have a hardware enable source (EN1 or EN2) or a software enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) source (SW). When enabled/disabled, the master sequencing timer generates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) eight sequencing events on different time periods called slots. The time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) period between each event is programmable within the configuration register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) Each regulator, GPIO1, GPIO2, GPIO3, and 32KHz clock has a flexible power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) sequence slave register which allows its enable source to be specified as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) a flexible power sequencer timer or a software bit. When a FPS source of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) regulators, GPIOs and clocks specifies the enable source to be a flexible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) power sequencer, the power up and power down delays can be specified in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) the regulators, GPIOs and clocks flexible power sequencer configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) When FPS event cleared (set to LOW), regulators, GPIOs and 32KHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) clock are set into following state at the sequencing event that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) corresponds to its flexible sequencer configuration register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) Sleep state: In this state, regulators, GPIOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) and 32KHz clock get disabled at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) the sequencing event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) Global Low Power Mode (GLPM): In this state, regulators are set in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) low power mode at the sequencing event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) The configuration parameters of FPS is provided through sub-node "fps"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) and their child for FPS specific. The child node name for FPS are "fps0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "fps1", and "fps2" for FPS0, FPS1 and FPS2 respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) The FPS configurations like FPS source, power up and power down slots for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) regulators, GPIOs and 32kHz clocks are provided in their respective
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) configuration nodes which is explained in respective sub-system DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) binding document.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) There is need for different FPS configuration parameters based on system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) state like when system state changed from active to suspend or active to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) power off (shutdown).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) -maxim,fps-event-source: u32, FPS event source like external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) hardware input to PMIC i.e. EN0, EN1 or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) software (SW).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) The macros are defined on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) dt-bindings/mfd/max77620.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) for different control source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) - MAX77620_FPS_EVENT_SRC_EN0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) for hardware input pin EN0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) - MAX77620_FPS_EVENT_SRC_EN1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) for hardware input pin EN1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) - MAX77620_FPS_EVENT_SRC_SW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) for software control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) -maxim,shutdown-fps-time-period-us: u32, FPS time period in microseconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) when system enters in to shutdown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) -maxim,suspend-fps-time-period-us: u32, FPS time period in microseconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) when system enters in to suspend state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) -maxim,device-state-on-disabled-event: u32, describe the PMIC state when FPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) event cleared (set to LOW) whether it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) should go to sleep state or low-power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) state. Following are valid values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) - MAX77620_FPS_INACTIVE_STATE_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) to set the PMIC state to sleep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) - MAX77620_FPS_INACTIVE_STATE_LOW_POWER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) to set the PMIC state to low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) power.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) Absence of this property or other value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) will not change device state when FPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) event get cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) Here supported time periods by device in microseconds are as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MAX77620 supports 40, 80, 160, 320, 640, 1280, 2560 and 5120 microseconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MAX20024 supports 20, 40, 80, 160, 320, 640, 1280 and 2540 microseconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MAX77663 supports 20, 40, 80, 160, 320, 640, 1280 and 2540 microseconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) -maxim,power-ok-control: configure map power ok bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 1: Enables POK(Power OK) to control nRST_IO and GPIO1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) POK function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 0: Disables POK control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if property missing, do not configure MPOK bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) If POK mapping is enabled for GPIO1/nRST_IO then,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) GPIO1/nRST_IO pins are HIGH only if all rails
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) that have POK control enabled are HIGH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) If any of the rails goes down(which are enabled for POK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) control) then, GPIO1/nRST_IO goes LOW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) this property is valid for max20024 only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) For DT binding details of different sub modules like GPIO, pincontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) regulator, power, please refer respective device-tree binding document
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) under their respective sub-system directories.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) --------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #include <dt-bindings/mfd/max77620.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) max77620@3c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) compatible = "maxim,max77620";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) reg = <0x3c>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) interrupt-parent = <&intc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) interrupts = <0 86 IRQ_TYPE_NONE>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) fps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) fps0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) maxim,shutdown-fps-time-period-us = <1280>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) fps1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) maxim,shutdown-fps-time-period-us = <1280>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) fps2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) maxim,shutdown-fps-time-period-us = <1280>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_SW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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