^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties for USART:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible: Should be one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - "atmel,at91rm9200-usart"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - "atmel,at91sam9260-usart"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - "microchip,sam9x60-usart"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - "microchip,sam9x60-dbgu", "microchip,sam9x60-usart"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - reg: Should contain registers location and length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - interrupts: Should contain interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - clock-names: tuple listing input clock names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Required elements: "usart"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - clocks: phandles to input clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Required properties for USART in SPI mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - #size-cells : Must be <0>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - #address-cells : Must be <1>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - cs-gpios: chipselects (internal cs not supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - atmel,usart-mode : Must be <AT91_USART_MODE_SPI> (found in dt-bindings/mfd/at91-usart.h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Optional properties in serial and SPI mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - dma bindings for dma transfer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - dmas: DMA specifier, consisting of a phandle to DMA controller node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) memory peripheral interface and USART DMA channel ID, FIFO configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) The order of DMA channels is fixed. The first DMA channel must be TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) associated channel and the second one must be RX associated channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Refer to dma.txt and atmel-dma.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - dma-names: "tx" for TX channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) "rx" for RX channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) The order of dma-names is also fixed. The first name must be "tx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) and the second one must be "rx" as in the examples below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Optional properties in serial mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - atmel,use-dma-rx: use of PDC or DMA for receiving data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - atmel,use-dma-tx: use of PDC or DMA for transmitting data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD line respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) It will use specified PIO instead of the peripheral function pin for the USART feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) If unsure, don't specify this property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) capable USARTs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - rs485-rts-delay, rs485-rx-during-tx, linux,rs485-enabled-at-boot-time: see rs485.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) <chip> compatible description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) - at91rm9200: legacy USART support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) - at91sam9260: generic USART implementation for SAM9 SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) - use PDC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) usart0: serial@fff8c000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) compatible = "atmel,at91sam9260-usart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) reg = <0xfff8c000 0x4000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) interrupts = <7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) clocks = <&usart0_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) clock-names = "usart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) atmel,use-dma-rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) atmel,use-dma-tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) rts-gpios = <&pioD 15 GPIO_ACTIVE_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) cts-gpios = <&pioD 16 GPIO_ACTIVE_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) dtr-gpios = <&pioD 17 GPIO_ACTIVE_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) dsr-gpios = <&pioD 18 GPIO_ACTIVE_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) dcd-gpios = <&pioD 20 GPIO_ACTIVE_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) rng-gpios = <&pioD 19 GPIO_ACTIVE_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) - use DMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) usart0: serial@f001c000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) compatible = "atmel,at91sam9260-usart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) reg = <0xf001c000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) interrupts = <12 4 5>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) clocks = <&usart0_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) clock-names = "usart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) atmel,use-dma-rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) atmel,use-dma-tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) dmas = <&dma0 2 0x3>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) <&dma0 2 0x204>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) dma-names = "tx", "rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) atmel,fifo-size = <32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) - SPI mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #include <dt-bindings/mfd/at91-usart.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) spi0: spi@f001c000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) compatible = "atmel,at91rm9200-usart", "atmel,at91sam9260-usart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) atmel,usart-mode = <AT91_USART_MODE_SPI>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) reg = <0xf001c000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) clocks = <&usart0_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) clock-names = "usart";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) dma-names = "tx", "rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) cs-gpios = <&pioB 3 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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