Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Device-Tree bindings for Atmel's HLCDC (High LCD Controller) MFD driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  - compatible: value should be one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)    "atmel,at91sam9n12-hlcdc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)    "atmel,at91sam9x5-hlcdc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)    "atmel,sama5d2-hlcdc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)    "atmel,sama5d3-hlcdc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)    "atmel,sama5d4-hlcdc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)    "microchip,sam9x60-hlcdc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  - reg: base address and size of the HLCDC device registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  - clock-names: the name of the 3 clocks requested by the HLCDC device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)    Should contain "periph_clk", "sys_clk" and "slow_clk".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  - clocks: should contain the 3 clocks requested by the HLCDC device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  - interrupts: should contain the description of the HLCDC interrupt line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) The HLCDC IP exposes two subdevices:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  - a PWM chip: see ../pwm/atmel-hlcdc-pwm.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  - a Display Controller: see ../display/atmel/hlcdc-dc.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	hlcdc: hlcdc@f0030000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		compatible = "atmel,sama5d3-hlcdc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		reg = <0xf0030000 0x2000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		clock-names = "periph_clk","sys_clk", "slow_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		hlcdc-display-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 			compatible = "atmel,hlcdc-display-controller";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 			pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 			pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 			#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 			#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 			port@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 				#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 				#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 				reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 				hlcdc_panel_output: endpoint@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 					reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 					remote-endpoint = <&panel_input>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 				};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		hlcdc_pwm: hlcdc-pwm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 			compatible = "atmel,hlcdc-pwm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 			pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			pinctrl-0 = <&pinctrl_lcd_pwm>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 			#pwm-cells = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	};