Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Device tree bindings for Atmel Flexcom (Flexible Serial Communication Unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) The Atmel Flexcom is just a wrapper which embeds a SPI controller, an I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) controller and an USART. Only one function can be used at a time and is chosen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) at boot time according to the device tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - compatible:		Should be "atmel,sama5d2-flexcom"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - reg:			Should be the offset/length value for Flexcom dedicated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 			I/O registers (without USART, TWI or SPI registers).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - clocks:		Should be the Flexcom peripheral clock from PMC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - #address-cells:	Should be <1>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - #size-cells:		Should be <1>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - ranges:		Should be one range for the full I/O register region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 			(including USART, TWI and SPI registers).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - atmel,flexcom-mode:	Should be one of the following values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 			- <1> for USART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 			- <2> for SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 			- <3> for I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Required child:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) A single available child device of type matching the "atmel,flexcom-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) The phandle provided by the clocks property of the child is the same as one for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) the Flexcom parent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) For other properties, please refer to the documentations of the respective
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - ../serial/atmel-usart.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - ../spi/spi_atmel.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - ../i2c/i2c-at91.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) flexcom@f8034000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	compatible = "atmel,sama5d2-flexcom";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	reg = <0xf8034000 0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	clocks = <&flx0_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	ranges = <0x0 0xf8034000 0x800>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	atmel,flexcom-mode = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	spi@400 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		compatible = "atmel,at91rm9200-spi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		reg = <0x400 0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		pinctrl-0 = <&pinctrl_flx0_default>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		clocks = <&flx0_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		clock-names = "spi_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		atmel,fifo-size = <32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		mtd_dataflash@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 			compatible = "atmel,at25f512b";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 			reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 			spi-max-frequency = <20000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };