^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) ======================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ======================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) primary use case of the Aspeed LPC controller is as a slave on the bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) (typically in a Baseboard Management Controller SoC), but under certain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) conditions it can also take the role of bus master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) The LPC controller is represented as a multi-function device to account for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) mix of functionality it provides. The principle split is between the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) layout at the start of the I/O space which is, to quote the Aspeed datasheet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) "basically compatible with the [LPC registers from the] popular BMC controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) H8S/2168[1]", and everything else, where everything else is an eclectic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) collection of functions with a esoteric register layout. "Everything else",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) here labeled the "host" portion of the controller, includes, but is not limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * An IPMI Block Transfer[2] Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * An LPC Host Controller: Manages LPC functions such as host vs slave mode, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) physical properties of some LPC pins, configuration of serial IRQs, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) APB-to-LPC bridging amonst other functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * An LPC Host Interface Controller: Manages functions exposed to the host such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) management and bus snoop configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * A set of SuperIO[3] scratch registers: Enables implementation of e.g. custom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) hardware management protocols for handover between the host and baseboard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) management controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Additionally the state of the LPC controller influences the pinmux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) configuration, therefore the host portion of the controller is exposed as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) syscon as a means to arbitrate access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) [0] http://www.intel.com/design/chipsets/industry/25128901.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) [1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) [2] https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) [3] https://en.wikipedia.org/wiki/Super_I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) Required properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ===================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) - compatible: One of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) "aspeed,ast2400-lpc", "simple-mfd"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "aspeed,ast2500-lpc", "simple-mfd"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) - reg: contains the physical address and length values of the Aspeed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) LPC memory region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) - #address-cells: <1>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) - #size-cells: <1>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) - ranges: Maps 0 to the physical address and length of the LPC memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) Required LPC Child nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ========================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) BMC Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) --------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) - compatible: One of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "aspeed,ast2400-lpc-bmc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "aspeed,ast2500-lpc-bmc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) - reg: contains the physical address and length values of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) H8S/2168-compatible LPC controller memory region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) Host Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ---------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) - compatible: One of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "aspeed,ast2400-lpc-host", "simple-mfd", "syscon"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) - reg: contains the address and length values of the host-related
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) register space for the Aspeed LPC controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) - #address-cells: <1>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) - #size-cells: <1>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) - ranges: Maps 0 to the address and length of the host-related LPC memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) lpc: lpc@1e789000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) compatible = "aspeed,ast2500-lpc", "simple-mfd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) reg = <0x1e789000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ranges = <0x0 0x1e789000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) lpc_bmc: lpc-bmc@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) compatible = "aspeed,ast2500-lpc-bmc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) reg = <0x0 0x80>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) lpc_host: lpc-host@80 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) reg = <0x80 0x1e0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) reg-io-width = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ranges = <0x0 0x80 0x1e0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) BMC Node Children
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ==================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) Host Node Children
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ==================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) LPC Host Interface Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) The LPC Host Interface Controller manages functions exposed to the host such as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) management and bus snoop configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) - compatible: One of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) "aspeed,ast2400-lpc-ctrl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) "aspeed,ast2500-lpc-ctrl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) - reg: contains offset/length values of the host interface controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) memory regions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) - clocks: contains a phandle to the syscon node describing the clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) There should then be one cell representing the clock to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) - memory-region: A phandle to a reserved_memory region to be used for the LPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) to AHB mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) - flash: A phandle to the SPI flash controller containing the flash to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) be exposed over the LPC to AHB mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) lpc-host@80 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) lpc_ctrl: lpc-ctrl@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) compatible = "aspeed,ast2500-lpc-ctrl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) reg = <0x0 0x80>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) memory-region = <&flash_memory>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) flash = <&spi>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) LPC Host Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) between the host and the baseboard management controller. The registers exist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) in the "host" portion of the Aspeed LPC controller, which must be the parent of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) the LPC host controller node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) - compatible: One of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) "aspeed,ast2400-lhc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) "aspeed,ast2500-lhc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) - reg: contains offset/length values of the LHC memory regions. In the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) AST2400 and AST2500 there are two regions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) lhc: lhc@20 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) compatible = "aspeed,ast2500-lhc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) reg = <0x20 0x24 0x48 0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) LPC reset control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) -----------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) The UARTs present in the ASPEED SoC can have their resets tied to the reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) state of the LPC bus. Some systems may chose to modify this configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) - compatible: "aspeed,ast2500-lpc-reset" or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "aspeed,ast2400-lpc-reset"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) - reg: offset and length of the IP in the LHC memory region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) - #reset-controller indicates the number of reset cells expected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) lpc_reset: reset-controller@18 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) compatible = "aspeed,ast2500-lpc-reset";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) reg = <0x18 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #reset-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags