^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Altera Arria10 Development Kit System Resource Chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required parent device properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible : "altr,a10sr"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - spi-max-frequency : Maximum SPI frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - reg : The SPI Chip Select address for the Arria10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) System Resource chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - interrupts : The interrupt line the device is connected to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - interrupt-controller : Marks the device node as an interrupt controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - #interrupt-cells : The number of cells to describe an IRQ, should be 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) The first cell is the IRQ number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) The second cell is the flags, encoded as trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) masks from ../interrupt-controller/interrupts.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) The A10SR consists of these sub-devices:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Device Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ------ ----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) a10sr_gpio GPIO Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) a10sr_rst Reset Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Arria10 GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - compatible : Should be "altr,a10sr-gpio"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - gpio-controller : Marks the device node as a GPIO Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - #gpio-cells : Should be two. The first cell is the pin number and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) the second cell is used to specify flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) See ../gpio/gpio.txt for more information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Arria10 Peripheral PHY Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - compatible : Should be "altr,a10sr-reset"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - #reset-cells : Should be one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) resource-manager@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) compatible = "altr,a10sr";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) spi-max-frequency = <100000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) interrupt-parent = <&portb>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) a10sr_gpio: gpio-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) compatible = "altr,a10sr-gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) a10sr_rst: reset-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) compatible = "altr,a10sr-reset";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #reset-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };