^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) STMicroelectronics STi c8sectpfe binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) ============================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) This document describes the c8sectpfe device bindings that is used to get transport
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) stream data into the SoC on the TS pins, and into DDR for further processing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) It is typically used in conjunction with one or more demodulator and tuner devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) which converts from the RF to digital domain. Demodulators and tuners are usually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) located on an external DVB frontend card connected to SoC TS input pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Currently 7 TS input (tsin) channels are supported on the stih407 family SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Required properties (controller (parent) node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - compatible : Should be "stih407-c8sectpfe"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - reg : Address and length of register sets for each device in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) "reg-names"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - reg-names : The names of the register addresses corresponding to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) registers filled in "reg":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - c8sectpfe: c8sectpfe registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - c8sectpfe-ram: c8sectpfe internal sram
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - clocks : phandle list of c8sectpfe clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - clock-names : should be "c8sectpfe"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) See: Documentation/devicetree/bindings/clock/clock-bindings.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - pinctrl-names : a pinctrl state named tsin%d-serial or tsin%d-parallel (where %d is tsin-num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) must be defined for each tsin child node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - pinctrl-0 : phandle referencing pin configuration for this tsin configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Required properties (tsin (child) node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - tsin-num : tsin id of the InputBlock (must be between 0 to 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - i2c-bus : phandle to the I2C bus DT node which the demodulators & tuners on this tsin channel are connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - reset-gpios : reset gpio for this tsin channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) Optional properties (tsin (child) node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - invert-ts-clk : Bool property to control sense of ts input clock (data stored on falling edge of clk).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - serial-not-parallel : Bool property to configure input bus width (serial on ts_data<7>).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - async-not-sync : Bool property to control if data is received in asynchronous mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) (all bits/bytes with ts_valid or ts_packet asserted are valid).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) - dvb-card : Describes the NIM card connected to this tsin channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* stih410 SoC b2120 + b2004a + stv0367-pll(NIMB) + stv0367-tda18212 (NIMA) DT example) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) c8sectpfe@8a20000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) compatible = "st,stih407-c8sectpfe";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) reg = <0x08a20000 0x10000>, <0x08a00000 0x4000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) reg-names = "stfe", "stfe-ram";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) interrupts = <GIC_SPI 34 IRQ_TYPE_NONE>, <GIC_SPI 35 IRQ_TYPE_NONE>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) interrupt-names = "stfe-error-irq", "stfe-idle-irq";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) pinctrl-0 = <&pinctrl_tsin0_serial>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) pinctrl-1 = <&pinctrl_tsin0_parallel>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) pinctrl-2 = <&pinctrl_tsin3_serial>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) pinctrl-3 = <&pinctrl_tsin4_serial_alt3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) pinctrl-4 = <&pinctrl_tsin5_serial_alt1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) pinctrl-names = "tsin0-serial",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "tsin0-parallel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "tsin3-serial",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "tsin4-serial",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "tsin5-serial";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) clocks = <&clk_s_c0_flexgen CLK_PROC_STFE>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) clock-names = "c8sectpfe";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* tsin0 is TSA on NIMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) tsin0: port@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) tsin-num = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) serial-not-parallel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) i2c-bus = <&ssc2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) reset-gpios = <&pio15 4 GPIO_ACTIVE_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) dvb-card = <STV0367_TDA18212_NIMA_1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) tsin3: port@3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) tsin-num = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) serial-not-parallel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) i2c-bus = <&ssc3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) reset-gpios = <&pio15 7 GPIO_ACTIVE_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) dvb-card = <STV0367_TDA18212_NIMB_1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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