^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Samsung S5P/Exynos SoC series MIPI CSI-2 receiver (MIPI CSIS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) -------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - compatible : "samsung,s5pv210-csis" for S5PV210 (S5PC110),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) "samsung,exynos4210-csis" for Exynos4210 (S5PC210),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) "samsung,exynos4212-csis" for Exynos4212/Exynos4412,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) "samsung,exynos5250-csis" for Exynos5250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - reg : offset and length of the register set for the device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - interrupts : should contain MIPI CSIS interrupt; the format of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) interrupt specifier depends on the interrupt controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - bus-width : maximum number of data lanes supported (SoC specific);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - vddio-supply : MIPI CSIS I/O and PLL voltage supply (e.g. 1.8V);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - vddcore-supply : MIPI CSIS Core voltage supply (e.g. 1.1V);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - clocks : list of clock specifiers, corresponding to entries in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) clock-names property;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - clock-names : must contain "csis", "sclk_csis" entries, matching entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) in the clocks property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - clock-frequency : The IP's main (system bus) clock frequency in Hz, default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) value when this property is not specified is 166 MHz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - samsung,csis-wclk : CSI-2 wrapper clock selection. If this property is present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) external clock from CMU will be used, or the bus clock if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) if it's not specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) The device node should contain one 'port' child node with one child 'endpoint'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) node, according to the bindings defined in Documentation/devicetree/bindings/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) media/video-interfaces.txt. The following are properties specific to those nodes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) port node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ---------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - reg : (required) must be 3 for camera C input (CSIS0) or 4 for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) camera D input (CSIS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) endpoint node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) -------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - data-lanes : (required) an array specifying active physical MIPI-CSI2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) data input lanes and their mapping to logical lanes; the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) array's content is unused, only its length is meaningful;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) - samsung,csis-hs-settle : (optional) differential receiver (HS-RX) settle time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) reg0: regulator@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) reg1: regulator@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* SoC properties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) csis_0: csis@11880000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) compatible = "samsung,exynos4210-csis";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) reg = <0x11880000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) interrupts = <0 78 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Board properties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) csis_0: csis@11880000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) clock-frequency = <166000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) vddio-supply = <®0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) vddcore-supply = <®1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) reg = <3>; /* 3 - CSIS0, 4 - CSIS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) csis0_ep: endpoint {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) remote-endpoint = <...>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) data-lanes = <1>, <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) samsung,csis-hs-settle = <12>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags