Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Samsung Multi Format Codec (MFC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Multi Format Codec (MFC) is the IP present in Samsung SoCs which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) supports high resolution decoding and encoding functionalities.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) The MFC device driver is a v4l2 driver which can encode/decode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) video raw/elementary streams and has support for all popular
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) video codecs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   - compatible : value should be either one among the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	(a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	(b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	(c) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	(d) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	(e) "samsung,exynos5433-mfc" for MFC v8 present in Exynos5433 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	(f) "samsung,mfc-v10" for MFC v10 present in Exynos7880 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   - reg : Physical base address of the IP registers and length of memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	  mapped region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   - interrupts : MFC interrupt number to the CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)   - clocks : from common clock binding: handle to mfc clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)   - clock-names : from common clock binding: must contain "mfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		  corresponding to entry in the clocks property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)   - power-domains : power-domain property defined with a phandle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 			   to respective power domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)   - memory-region : from reserved memory binding: phandles to two reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	memory regions, first is for "left" mfc memory bus interfaces,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	second if for the "right" mfc memory bus, used when no SYSMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	support is available; used only by MFC v5 present in Exynos4 SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Obsolete properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)   - samsung,mfc-r, samsung,mfc-l : support removed, please use memory-region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	property instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) SoC specific DT entry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) mfc: codec@13400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	compatible = "samsung,mfc-v5";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	reg = <0x13400000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	interrupts = <0 94 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	power-domains = <&pd_mfc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	clocks = <&clock 273>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	clock-names = "mfc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) Reserved memory specific DT entry for given board (see reserved memory binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) for more information):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) reserved-memory {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	mfc_left: region@51000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		compatible = "shared-dma-pool";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		no-map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		reg = <0x51000000 0x800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	mfc_right: region@43000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		compatible = "shared-dma-pool";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		no-map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 		reg = <0x43000000 0x800000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) Board specific DT entry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) codec@13400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	memory-region = <&mfc_left>, <&mfc_right>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };