Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) $id: "http://devicetree.org/schemas/media/rockchip-vpu.yaml#"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) $schema: "http://devicetree.org/meta-schemas/core.yaml#"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) title: Hantro G1 VPU codecs implemented on Rockchip SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   - Ezequiel Garcia <ezequiel@collabora.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   Hantro G1 video encode and decode accelerators present on Rockchip SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)     enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)       - rockchip,rk3288-vpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)       - rockchip,rk3328-vpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)       - rockchip,rk3399-vpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)   reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)   interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)     minItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)     maxItems: 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)   interrupt-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)     oneOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)       - const: vdpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)       - items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)           - const: vepu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)           - const: vdpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)   clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)     maxItems: 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)   clock-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)       - const: aclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)       - const: hclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)   power-domains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)   iommus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)   - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)   - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)   - interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)   - interrupt-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)   - clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)   - clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)   - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)         #include <dt-bindings/clock/rk3288-cru.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)         #include <dt-bindings/interrupt-controller/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)         #include <dt-bindings/power/rk3288-power.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)         vpu: video-codec@ff9a0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)                 compatible = "rockchip,rk3288-vpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)                 reg = <0xff9a0000 0x800>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)                 interrupt-names = "vepu", "vdpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)                 clock-names = "aclk", "hclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)                 power-domains = <&power RK3288_PD_VIDEO>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)                 iommus = <&vpu_mmu>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)         };