Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) # SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) $id: http://devicetree.org/schemas/media/rockchip-rga.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) title: Rockchip 2D raster graphic acceleration controller (RGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   RGA is a standalone 2D raster graphic acceleration unit. It accelerates 2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   graphics operations, such as point/line drawing, image scaling, rotation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)   BitBLT, alpha blending and image blur/sharpness.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   - Jacob Chen <jacob-chen@iotwrt.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   - Ezequiel Garcia <ezequiel@collabora.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)   compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)     oneOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)       - const: rockchip,rk3288-rga
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)       - const: rockchip,rk3399-rga
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)       - items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)           - const: rockchip,rk3228-rga
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)           - const: rockchip,rk3288-rga
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)   reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)   interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)   clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)     maxItems: 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)   clock-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)       - const: aclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)       - const: hclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)       - const: sclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)   power-domains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)   resets:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)     maxItems: 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)   reset-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)     items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)       - const: core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)       - const: axi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)       - const: ahb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)   - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)   - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)   - interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)   - clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)   - clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)   - resets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)   - reset-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) additionalProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)   - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)     #include <dt-bindings/clock/rk3399-cru.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)     #include <dt-bindings/interrupt-controller/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)     #include <dt-bindings/power/rk3399-power.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)     rga: rga@ff680000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)       compatible = "rockchip,rk3399-rga";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)       reg = <0xff680000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)       interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)       clocks = <&cru ACLK_RGA>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)                <&cru HCLK_RGA>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)                <&cru SCLK_RGA_CORE>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)       clock-names = "aclk", "hclk", "sclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)       power-domains = <&power RK3399_PD_RGA>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)       resets = <&cru SRST_RGA_CORE>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)                <&cru SRST_A_RGA>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)                <&cru SRST_H_RGA>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)       reset-names = "core", "axi", "ahb";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)     };