^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Rockchip SoC MIPI RX D-PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) -------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - compatible: value should be one of the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) "rockchip,rk1808-mipi-dphy-rx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) "rockchip,rk3288-mipi-dphy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) "rockchip,rk3326-mipi-dphy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) "rockchip,rk3368-mipi-dphy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) "rockchip,rk3399-mipi-dphy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) "rockchip,rv1126-csi-dphy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - clocks : list of clock specifiers, corresponding to entries in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) clock-names property;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - clock-names: required clock name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) MIPI RX0 D-PHY use registers in "general register files", it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) should be a child of the GRF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) MIPI TX1RX1 D-PHY have its own registers, it must have a reg property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - reg: offset and length of the register set for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - rockchip,grf: MIPI TX1RX1 D-PHY not only has its own register but also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) the GRF, so it is only necessary for MIPI TX1RX1 D-PHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) port node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) The device node should contain two 'port' child nodes, according to the bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) defined in Documentation/devicetree/bindings/media/video-interfaces.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) The first port show the sensors connected in this mipi-dphy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - endpoint:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - remote-endpoint: Linked to a sensor with a MIPI CSI-2 video bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - data-lanes : (required) an array specifying active physical MIPI-CSI2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) data input lanes and their mapping to logical lanes; the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) D-PHY can't reroute lanes, so the array's content should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) be consecutive and only its length is meaningful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) For CCP2, v4l2 fwnode endpoint parse this read by u32.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - bus-type: data bus type. Possible values are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 0 - autodetect based on other properties (MIPI CSI-2 D-PHY, parallel or Bt656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 1 - MIPI CSI-2 C-PHY, no support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 2 - MIPI CSI1, no support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 3 - CCP2, using for lvds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) The port node must contain at least one endpoint. It could have multiple endpoints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) linked to different sensors, but please note that they are not supposed to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) actived at the same time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) The second port should be connected to isp node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) - endpoint:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) - remote-endpoint: Linked to Rockchip ISP1, which is defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) in rockchip-isp1.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) Device node example
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) grf: syscon@ff770000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) mipi_dphy_rx0: mipi-dphy-rx0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) compatible = "rockchip,rk3399-mipi-dphy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) clocks = <&cru SCLK_MIPIDPHY_REF>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) <&cru SCLK_DPHY_RX0_CFG>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) <&cru PCLK_VIO_GRF>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) clock-names = "dphy-ref", "dphy-cfg", "grf";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) power-domains = <&power RK3399_PD_VIO>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ports {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) port@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) mipi_in_wcam: endpoint@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) remote-endpoint = <&wcam_out>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) data-lanes = <1 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) mipi_in_ucam: endpoint@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) remote-endpoint = <&ucam_out>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) data-lanes = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) port@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dphy_rx0_out: endpoint {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) remote-endpoint = <&isp0_mipi_in>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) example for rv1126 node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) csi_dphy0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) compatible = "rockchip,rv1126-csi-dphy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) reg = <0xff4b0000 0x8000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) clocks = <&cru PCLK_CSIPHY0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) clock-names = "pclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) rockchip,grf = <&grf>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) status = "okay";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ports {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) port@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) mipi_in_ucam0: endpoint@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) remote-endpoint = <&ucam_out0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*data-lanes = <1 2 3 4>; //for mipi*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) data-lanes = <4>; //for lvds, note: this diff to mipi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) bus-type = <3>; //for lvds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) port@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) csidphy0_out: endpoint@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) remote-endpoint = <&isp_in>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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