^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Rockchip SoC Camera Interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) ----------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Rockchip CIF is a camera interface for the Rockchip series of SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) like px30, rk3288, rk312x, rk1808, RV1108 to receive frame data from camera or CCIR656 encoder,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) and transfer the data into system main memory by AXI bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - compatible: value should be one of the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) "rockchip,px30-cif";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) "rockchip,rk1808-cif";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) "rockchip,rk3128-cif";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) "rockchip,rk3288-cif";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - reg : offset and length of the register set for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - interrupts: should contain cif interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - clocks: phandle to the required clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - clock-names: required clock name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - iommus: iommu node attached to cif if exist.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - resets: CRU reset of cif if exist.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) port node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) The device node should contain one 'port' child node with child 'endpoint'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) nodes, according to the bindings defined in Documentation/devicetree/bindings/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) media/video-interfaces.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - endpoint(parallel):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - remote-endpoint: Connecting to a sensor with a parallel video bus or a mipi csi2 bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - parallel_bus properties: Refer to Documentation/devicetree/bindings/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) media/video-interfaces.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - mipi csi2 bus properties: Refer to Documentation/devicetree/bindings/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) media/video-interfaces.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) The port node must contain at least one endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) It could have multiple endpoints, but please note the hardware don't support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) two sensors work at a time, they are supposed to work asynchronously.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Device node example
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) -------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) cif: cif@ff490000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) compatible = "rockchip,px30-cif";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) reg = <0x0 0xff490000 0x0 0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>, <&cru SCLK_CIF_OUT>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) clock-names = "aclk_cif", "hclk_cif", "pclk_cif", "cif_out";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_pclkin";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) power-domains = <&power PX30_PD_VI>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) iommus = <&vip_mmu>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) status = "okay";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) cif_in: endpoint {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) remote-endpoint = <&gc2155_out>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) vsync-active = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) hsync-active = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) cif: cif@ffae0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) compatible = "rockchip,rk1808-cif";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) reg = <0x0 0xffae0000 0x0 0x200>, <0x0 0xffb10000 0x0 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) reg-names = "cif_regs", "csihost_regs";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) clocks = <&cru ACLK_CIF>, <&cru DCLK_CIF>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) <&cru HCLK_CIF>, <&cru SCLK_CIF_OUT>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) <&cru PCLK_CSI2HOST>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) clock-names = "aclk_cif", "dclk_cif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) "hclk_cif", "sclk_cif_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "pclk_csi2host";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) <&cru SRST_CIF_I>, <&cru SRST_CIF_D>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) <&cru SRST_CIF_PCLKIN>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) reset-names = "rst_cif_a", "rst_cif_h",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "rst_cif_i", "rst_cif_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "rst_cif_pclkin";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) power-domains = <&power RK1808_PD_VIO>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) iommus = <&cif_mmu>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) status = "okay";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) cif_in: endpoint@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) remote-endpoint = <&dphy_rx_out>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) data-lanes = <1 2 3 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) cif: cif@1010a000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) compatible = "rockchip,rk3128-cif";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) reg = <0x1010a000 0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) <&cru SCLK_CIF_OUT>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) clock-names = "aclk_cif", "hclk_cif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "sclk_cif_out";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) resets = <&cru SRST_CIF0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) reset-names = "rst_cif";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* px3se has not iommu attached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* iommus = <&cif_mmu>; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) power-domains = <&power RK3128_PD_VIO>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) status = "okay";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) cif_in: endpoint {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) remote-endpoint = <&adv7181_out>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) vsync-active = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) hsync-active = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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