Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Marvell PXA camera host interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  - compatible: Should be "marvell,pxa270-qci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  - reg: register base and size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  - interrupts: the interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  - any required generic properties defined in video-interfaces.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  - clocks: input clock (see clock-bindings.txt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  - clock-output-names: should contain the name of the clock driving the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)                        sensor master clock MCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  - clock-frequency: host interface is driving MCLK, and MCLK rate is this rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	pxa_camera: pxa_camera@50000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		compatible = "marvell,pxa270-qci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		reg = <0x50000000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		interrupts = <33>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		clocks = <&pxa2xx_clks 24>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		clock-names = "ciclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		clock-frequency = <50000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		clock-output-names = "qci_mclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 			#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 			#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 			/* Parallel bus endpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 			qci: endpoint@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 				reg = <0>;		/* Local endpoint # */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 				remote-endpoint = <&mt9m111_1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 				bus-width = <8>;	/* Used data lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 				hsync-active = <0>;	/* Active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 				vsync-active = <0>;	/* Active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 				pclk-sample = <1>;	/* Rising */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	};