^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Device-Tree bindings for Mediatek consumer IR controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) found in Mediatek SoC family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - compatible : Should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) "mediatek,mt7623-cir": for MT7623 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) "mediatek,mt7622-cir": for MT7622 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - clocks : list of clock specifiers, corresponding to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) entries in clock-names property;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - clock-names : should contain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - "clk" entries: for MT7623 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - "clk", "bus" entries: for MT7622 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - interrupts : should contain IR IRQ number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - reg : should contain IO map address for IR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - linux,rc-map-name : see rc.txt file in the same directory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) cir: cir@10013000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) compatible = "mediatek,mt7623-cir";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) reg = <0 0x10013000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) clocks = <&infracfg CLK_INFRA_IRRX>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) clock-names = "clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) linux,rc-map-name = "rc-rc6-mce";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };