Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Mediatek Video Processor Unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Video Processor Unit is a HW video controller. It controls HW Codec including
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) H.264/VP8/VP9 Decode, H.264/VP8 Encode and Image Processor (scale/rotate/color convert).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)   - compatible: "mediatek,mt8173-vpu"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)   - reg: Must contain an entry for each entry in reg-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)   - reg-names: Must include the following entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)     "tcm": tcm base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)     "cfg_reg": Main configuration registers base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)   - interrupts: interrupt number to the cpu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   - clocks : clock name from clock manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   - clock-names: must be main. It is the main clock of VPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   - memory-region: phandle to a node describing memory (see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)     Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)     to be used for VPU extended memory; if not present, VPU may be located
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)     anywhere in the memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	vpu: vpu@10020000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		compatible = "mediatek,mt8173-vpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		reg = <0 0x10020000 0 0x30000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		      <0 0x10050000 0 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		reg-names = "tcm", "cfg_reg";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		clocks = <&topckgen TOP_SCP_SEL>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		clock-names = "main";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	};