^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Mediatek Video Codec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Mediatek Video Codec is the video codec hw present in Mediatek SoCs which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) supports high resolution encoding and decoding functionalities.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - compatible : "mediatek,mt8173-vcodec-enc" for MT8173 encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) "mediatek,mt8183-vcodec-enc" for MT8183 encoder.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) "mediatek,mt8173-vcodec-dec" for MT8173 decoder.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - reg : Physical base address of the video codec registers and length of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) memory mapped region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - interrupts : interrupt number to the cpu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - mediatek,larb : must contain the local arbiters in the current Socs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - clocks : list of clock specifiers, corresponding to entries in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) the clock-names property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - clock-names: encoder must contain "venc_sel_src", "venc_sel",,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) "venc_lt_sel_src", "venc_lt_sel", decoder must contain "vcodecpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) "univpll_d2", "clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) "venc_lt_sel", "vdec_bus_clk_src".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - iommus : should point to the respective IOMMU block with master port as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) One of the two following nodes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - mediatek,vpu : the node of the video processor unit, if using VPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - mediatek,scp : the node of the SCP unit, if using SCP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) vcodec_dec: vcodec@16000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) compatible = "mediatek,mt8173-vcodec-dec";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) reg = <0 0x16000000 0 0x100>, /*VDEC_SYS*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) <0 0x16020000 0 0x1000>, /*VDEC_MISC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) <0 0x16021000 0 0x800>, /*VDEC_LD*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) <0 0x16021800 0 0x800>, /*VDEC_TOP*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) <0 0x16022000 0 0x1000>, /*VDEC_CM*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) <0 0x16023000 0 0x1000>, /*VDEC_AD*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) <0 0x16024000 0 0x1000>, /*VDEC_AV*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) <0 0x16025000 0 0x1000>, /*VDEC_PP*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) <0 0x16026800 0 0x800>, /*VP8_VD*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) <0 0x16027000 0 0x800>, /*VP6_VD*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) <0 0x16027800 0 0x800>, /*VP8_VL*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) <0 0x16028400 0 0x400>; /*VP9_VD*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) mediatek,larb = <&larb1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) mediatek,vpu = <&vpu>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) <&topckgen CLK_TOP_UNIVPLL_D2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) <&topckgen CLK_TOP_CCI400_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) <&topckgen CLK_TOP_VDEC_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) <&topckgen CLK_TOP_VCODECPLL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) <&apmixedsys CLK_APMIXED_VENCPLL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) <&topckgen CLK_TOP_VENC_LT_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) <&topckgen CLK_TOP_VCODECPLL_370P5>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) clock-names = "vcodecpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "univpll_d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "clk_cci400_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "vdec_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "vdecpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "vencpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "venc_lt_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "vdec_bus_clk_src";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) <&topckgen CLK_TOP_CCI400_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) <&topckgen CLK_TOP_VDEC_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) <&apmixedsys CLK_APMIXED_VCODECPLL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) <&apmixedsys CLK_APMIXED_VENCPLL>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) <&topckgen CLK_TOP_UNIVPLL_D2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) <&topckgen CLK_TOP_VCODECPLL>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) vcodec_enc: vcodec@18002000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) compatible = "mediatek,mt8173-vcodec-enc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) reg = <0 0x18002000 0 0x1000>, /*VENC_SYS*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) <0 0x19002000 0 0x1000>; /*VENC_LT_SYS*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) mediatek,larb = <&larb3>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) <&larb5>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) iommus = <&iommu M4U_PORT_VENC_RCPU>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) <&iommu M4U_PORT_VENC_REC>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) <&iommu M4U_PORT_VENC_BSDMA>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) <&iommu M4U_PORT_VENC_SV_COMV>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) <&iommu M4U_PORT_VENC_RD_COMV>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) <&iommu M4U_PORT_VENC_CUR_LUMA>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) <&iommu M4U_PORT_VENC_CUR_CHROMA>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) <&iommu M4U_PORT_VENC_REF_LUMA>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) <&iommu M4U_PORT_VENC_REF_CHROMA>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) <&iommu M4U_PORT_VENC_NBM_RDMA>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) <&iommu M4U_PORT_VENC_NBM_WDMA>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) <&iommu M4U_PORT_VENC_RCPU_SET2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) <&iommu M4U_PORT_VENC_BSDMA_SET2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) mediatek,vpu = <&vpu>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) <&topckgen CLK_TOP_VENC_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) <&topckgen CLK_TOP_UNIVPLL1_D2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) <&topckgen CLK_TOP_VENC_LT_SEL>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) clock-names = "venc_sel_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "venc_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "venc_lt_sel_src",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "venc_lt_sel";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) <&topckgen CLK_TOP_VENC_LT_SEL>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) <&topckgen CLK_TOP_UNIVPLL1_D2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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