^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Mediatek Media Data Path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Media Data Path is used for scaling and color space conversion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Required properties (controller node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - compatible: "mediatek,mt8173-mdp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - mediatek,vpu: the node of video processor unit, see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Documentation/devicetree/bindings/media/mediatek-vpu.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Required properties (all function blocks, child node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - compatible: Should be one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) "mediatek,mt8173-mdp-rdma" - read DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) "mediatek,mt8173-mdp-rsz" - resizer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) "mediatek,mt8173-mdp-wdma" - write DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) "mediatek,mt8173-mdp-wrot" - write DMA with rotation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - reg: Physical base address and length of the function block register space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - clocks: device clocks, see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - power-domains: a phandle to the power domain, see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Documentation/devicetree/bindings/power/power_domain.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Required properties (DMA function blocks, child node):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - compatible: Should be one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) "mediatek,mt8173-mdp-rdma"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) "mediatek,mt8173-mdp-wdma"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) "mediatek,mt8173-mdp-wrot"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - iommus: should point to the respective IOMMU block with master port as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - mediatek,larb: must contain the local arbiters in the current Socs, see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) mdp_rdma0: rdma@14001000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) compatible = "mediatek,mt8173-mdp-rdma";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) "mediatek,mt8173-mdp";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) reg = <0 0x14001000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) clocks = <&mmsys CLK_MM_MDP_RDMA0>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) <&mmsys CLK_MM_MUTEX_32K>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) iommus = <&iommu M4U_PORT_MDP_RDMA0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) mediatek,larb = <&larb0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) mediatek,vpu = <&vpu>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) mdp_rdma1: rdma@14002000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) compatible = "mediatek,mt8173-mdp-rdma";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) reg = <0 0x14002000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) clocks = <&mmsys CLK_MM_MDP_RDMA1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) <&mmsys CLK_MM_MUTEX_32K>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) iommus = <&iommu M4U_PORT_MDP_RDMA1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) mediatek,larb = <&larb4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mdp_rsz0: rsz@14003000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) compatible = "mediatek,mt8173-mdp-rsz";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) reg = <0 0x14003000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) clocks = <&mmsys CLK_MM_MDP_RSZ0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) mdp_rsz1: rsz@14004000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) compatible = "mediatek,mt8173-mdp-rsz";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) reg = <0 0x14004000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) clocks = <&mmsys CLK_MM_MDP_RSZ1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) mdp_rsz2: rsz@14005000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) compatible = "mediatek,mt8173-mdp-rsz";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) reg = <0 0x14005000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) clocks = <&mmsys CLK_MM_MDP_RSZ2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) mdp_wdma0: wdma@14006000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) compatible = "mediatek,mt8173-mdp-wdma";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) reg = <0 0x14006000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) clocks = <&mmsys CLK_MM_MDP_WDMA>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) iommus = <&iommu M4U_PORT_MDP_WDMA>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) mediatek,larb = <&larb0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) mdp_wrot0: wrot@14007000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) compatible = "mediatek,mt8173-mdp-wrot";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) reg = <0 0x14007000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) clocks = <&mmsys CLK_MM_MDP_WROT0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) iommus = <&iommu M4U_PORT_MDP_WROT0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) mediatek,larb = <&larb0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) mdp_wrot1: wrot@14008000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) compatible = "mediatek,mt8173-mdp-wrot";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) reg = <0 0x14008000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) clocks = <&mmsys CLK_MM_MDP_WROT1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) iommus = <&iommu M4U_PORT_MDP_WROT1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) mediatek,larb = <&larb4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags