Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * MediaTek JPEG Encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - compatible : "mediatek,mt2701-jpgenc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)   followed by "mediatek,mtk-jpgenc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - reg : physical base address of the JPEG encoder registers and length of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)   memory mapped region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - interrupts : interrupt number to the interrupt controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - clocks: device clocks, see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)   Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - clock-names: must contain "jpgenc". It is the clock of JPEG encoder.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - power-domains: a phandle to the power domain, see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   Documentation/devicetree/bindings/power/power_domain.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - mediatek,larb: must contain the local arbiters in the current SoCs, see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - iommus: should point to the respective IOMMU block with master port as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)   argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	jpegenc: jpegenc@1500a000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		compatible = "mediatek,mt2701-jpgenc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 			     "mediatek,mtk-jpgenc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		reg = <0 0x1500a000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		clocks =  <&imgsys CLK_IMG_VENC>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		clock-names = "jpgenc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		mediatek,larb = <&larb2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 			 <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	};