Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Mediatek JPEG Decoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Mediatek JPEG Decoder is the JPEG decode hardware present in Mediatek SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - compatible : must be one of the following string:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	"mediatek,mt8173-jpgdec"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 	"mediatek,mt7623-jpgdec", "mediatek,mt2701-jpgdec"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 	"mediatek,mt2701-jpgdec"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - reg : physical base address of the jpeg decoder registers and length of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   memory mapped region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - interrupts : interrupt number to the interrupt controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - clocks: device clocks, see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - clock-names: must contain "jpgdec-smi" and "jpgdec".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - power-domains: a phandle to the power domain, see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   Documentation/devicetree/bindings/power/power_domain.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - mediatek,larb: must contain the local arbiters in the current Socs, see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)   Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)   for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - iommus: should point to the respective IOMMU block with master port as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)   argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)   for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	jpegdec: jpegdec@15004000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		compatible = "mediatek,mt2701-jpgdec";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		reg = <0 0x15004000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		clocks =  <&imgsys CLK_IMG_JPGDEC_SMI>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 			  <&imgsys CLK_IMG_JPGDEC>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		clock-names = "jpgdec-smi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 			      "jpgdec";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		mediatek,larb = <&larb2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 			 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	};