Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Freescale i.MX Media Video Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) =================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Video Media Controller node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) ---------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) This is the media controller node for video capture support. It is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) virtual device that lists the camera serial interface nodes that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) media device will control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - compatible : "fsl,imx-capture-subsystem";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - ports      : Should contain a list of phandles pointing to camera
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 		sensor interface ports of IPU devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) capture-subsystem {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	compatible = "fsl,imx-capture-subsystem";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	ports = <&ipu1_csi0>, <&ipu1_csi1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) mipi_csi2 node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) --------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) This is the device node for the MIPI CSI-2 Receiver core in the i.MX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) SoC. This is a Synopsys Designware MIPI CSI-2 host controller core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) combined with a D-PHY core mixed into the same register block. In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) addition this device consists of an i.MX-specific "CSI2IPU gasket"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) glue logic, also controlled from the same register block. The CSI2IPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) gasket demultiplexes the four virtual channel streams from the host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) controller's 32-bit output image bus onto four 16-bit parallel busses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) to the i.MX IPU CSIs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - compatible	: "fsl,imx6-mipi-csi2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - reg           : physical base address and length of the register set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - clocks	: the MIPI CSI-2 receiver requires three clocks: hsi_tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		  (the D-PHY clock), video_27m (D-PHY PLL reference
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		  clock), and eim_podf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - clock-names	: must contain "dphy", "ref", "pix";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - port@*        : five port nodes must exist, containing endpoints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		  connecting to the source and sink devices according to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		  of_graph bindings. The first port is an input port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		  connecting with a MIPI CSI-2 source, and ports 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		  through 4 are output ports connecting with parallel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		  bus sink endpoint nodes and correspond to the four
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		  MIPI CSI-2 virtual channel outputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) - interrupts	: must contain two level-triggered interrupts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		  in order: 100 and 101;