^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * ImgTec Infrared (IR) decoder version 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) This binding is for Imagination Technologies' Infrared decoder block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) specifically major revision 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - compatible: Should be "img,ir-rev1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - reg: Physical base address of the controller and length of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) memory mapped region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - interrupts: The interrupt specifier to the cpu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - clocks: List of clock specifiers as described in standard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) clock bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Up to 3 clocks may be specified in the following order:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 1st: Core clock (defaults to 32.768KHz if omitted).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 2nd: System side (fast) clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 3rd: Power modulation clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - clock-names: List of clock names corresponding to the clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) specified in the clocks property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Accepted clock names are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) "core": Core clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) "sys": System clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) "mod": Power modulation clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ir@2006200 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) compatible = "img,ir-rev1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) reg = <0x02006200 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) interrupts = <29 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) clocks = <&clk_32khz>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) clock-names = "core";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };