^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Freescale Pixel Pipeline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) ========================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) that supports scaling, colorspace conversion, alpha blending, rotation, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) pixel conversion via lookup table. Different versions are present on various
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) i.MX SoCs from i.MX23 to i.MX7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - compatible: should be "fsl,<soc>-pxp", where SoC can be one of imx23, imx28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) imx6dl, imx6sl, imx6sll, imx6ul, imx6sx, imx6ull, or imx7d.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - reg: the register base and size for the device registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - interrupts: the PXP interrupt, two interrupts for imx6ull and imx7d.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - clock-names: should be "axi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - clocks: the PXP AXI clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) pxp@21cc000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) compatible = "fsl,imx6ull-pxp";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) reg = <0x021cc000 0x4000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) clock-names = "axi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) clocks = <&clks IMX6UL_CLK_PXP>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };