Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Chips&Media Coda multi-standard codec IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) ========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Coda codec IPs are present in i.MX SoCs in various versions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) called VPU (Video Processing Unit).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - compatible : should be "fsl,<chip>-src" for i.MX SoCs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)   (a) "fsl,imx27-vpu" for CodaDx6 present in i.MX27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   (b) "fsl,imx51-vpu" for CodaHx4 present in i.MX51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   (c) "fsl,imx53-vpu" for CODA7541 present in i.MX53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)   (d) "fsl,imx6q-vpu" for CODA960 present in i.MX6q
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - reg: should be register base and length as documented in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   SoC reference manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - interrupts : Should contain the VPU interrupt. For CODA960,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   a second interrupt is needed for the MJPEG unit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - clocks : Should contain the ahb and per clocks, in the order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   determined by the clock-names property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - clock-names : Should be "ahb", "per"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - iram : phandle pointing to the SRAM device node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) vpu: vpu@63ff4000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	compatible = "fsl,imx53-vpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	reg = <0x63ff4000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	interrupts = <9>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	clocks = <&clks 63>, <&clks 63>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	clock-names = "ahb", "per";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	iram = <&ocram>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };