^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) OMAP2+ and K3 Mailbox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) =====================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) The OMAP mailbox hardware facilitates communication between different processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) using a queued mailbox interrupt mechanism. The IP block is external to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) various processor subsystems and is connected on an interconnect bus. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) communication is achieved through a set of registers for message storage and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) interrupt configuration registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Each mailbox IP block/cluster has a certain number of h/w fifo queues and output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) interrupt lines. An output interrupt line is routed to an interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) within a processor subsystem, and there can be more than one line going to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) specific processor's interrupt controller. The interrupt line connections are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) fixed for an instance and are dictated by the IP integration into the SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) (excluding the SoCs that have a Interrupt Crossbar IP). Each interrupt line is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) programmable through a set of interrupt configuration registers, and have a rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) and tx interrupt source per h/w fifo. Communication between different processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) is achieved through the appropriate programming of the rx and tx interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) sources on the appropriate interrupt lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) The number of h/w fifo queues and interrupt lines dictate the usable registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) All the current OMAP SoCs except for the newest DRA7xx SoC has a single IP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) instance. DRA7xx has multiple instances with different number of h/w fifo queues
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) and interrupt lines between different instances. The interrupt lines can also be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) routed to different processor sub-systems on DRA7xx as they are routed through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) the Crossbar, a kind of interrupt router/multiplexer. The K3 AM65x and J721E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) SoCs has each of these instances form a cluster and combine multiple clusters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) into a single IP block present within the Main NavSS. The interrupt lines from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) all these clusters are multiplexed and routed to different processor subsystems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) over a limited number of common interrupt output lines of an Interrupt Router.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) Mailbox Device Node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ====================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) A Mailbox device node is used to represent a Mailbox IP instance/cluster within
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) a SoC. The sub-mailboxes are represented as child nodes of this parent node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) --------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - compatible: Should be one of the following,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) "ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) AM43xx and DRA7xx SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "ti,am654-mailbox" for K3 AM65x and J721E SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - reg: Contains the mailbox register address range (base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) address and length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) - interrupts: Contains the interrupt information for the mailbox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) device. The format is dependent on which interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) controller the Mailbox device uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) - #mbox-cells: Common mailbox binding property to identify the number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) of cells required for the mailbox specifier. Should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) - ti,mbox-num-users: Number of targets (processor devices) that the mailbox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) device can interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) - ti,mbox-num-fifos: Number of h/w fifo queues within the mailbox IP block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) SoC-specific Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ---------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) The following are mandatory properties for the OMAP architecture based SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) only:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) - ti,hwmods: Name of the hwmod associated with the mailbox. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) should be defined in the mailbox node only if the node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) is not defined as a child node of a corresponding sysc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) interconnect node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) The following are mandatory properties for the K3 AM65x and J721E SoCs only:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) - interrupt-parent: Should contain a phandle to the TI-SCI interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) controller node that is used to dynamically program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) the interrupt routes between the IP and the main GIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) controllers. See the following binding for additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) details,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) Child Nodes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) A child node is used for representing the actual sub-mailbox device that is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) used for the communication between the host processor and a remote processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) Each child node should have a unique node name across all the different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) mailbox device nodes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) --------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) - ti,mbox-tx: sub-mailbox descriptor property defining a Tx fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) - ti,mbox-rx: sub-mailbox descriptor property defining a Rx fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) Sub-mailbox Descriptor Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ---------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) Each of the above ti,mbox-tx and ti,mbox-rx properties should have 3 cells of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) data that represent the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) Cell #1 (fifo_id) - mailbox fifo id used either for transmitting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) (ti,mbox-tx) or for receiving (ti,mbox-rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) Cell #2 (irq_id) - irq identifier index number to use from the parent's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) interrupts data. Should be 0 for most of the cases, a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) positive index value is seen only on mailboxes that have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) multiple interrupt lines connected to the MPU processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) Cell #3 (usr_id) - mailbox user id for identifying the interrupt line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) associated with generating a tx/rx fifo interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) Optional Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) --------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) - ti,mbox-send-noirq: Quirk flag to allow the client user of this sub-mailbox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) to send messages without triggering a Tx ready interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) and to control the Tx ticker. Should be used only on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) sub-mailboxes used to communicate with WkupM3 remote
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) processor on AM33xx/AM43xx SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) Mailbox Users:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ==============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) A device needing to communicate with a target processor device should specify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) them using the common mailbox binding properties, "mboxes" and the optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) for details). Each value of the mboxes property should contain a phandle to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) mailbox controller device node and an args specifier that will be the phandle to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) the intended sub-mailbox child node to be used for communication. The equivalent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "mbox-names" property value can be used to give a name to the communication channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) to be used by the client user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) --------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 1. /* OMAP4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) mailbox: mailbox@4a0f4000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) compatible = "ti,omap4-mailbox";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) reg = <0x4a0f4000 0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ti,hwmods = "mailbox";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #mbox-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ti,mbox-num-users = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ti,mbox-num-fifos = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) mbox_ipu: mbox_ipu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ti,mbox-tx = <0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ti,mbox-rx = <1 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) mbox_dsp: mbox_dsp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ti,mbox-tx = <3 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ti,mbox-rx = <2 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dsp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) mboxes = <&mailbox &mbox_dsp>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 2. /* AM33xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) mailbox: mailbox@480c8000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) compatible = "ti,omap4-mailbox";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) reg = <0x480C8000 0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) interrupts = <77>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ti,hwmods = "mailbox";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #mbox-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ti,mbox-num-users = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ti,mbox-num-fifos = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) mbox_wkupm3: wkup_m3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ti,mbox-tx = <0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ti,mbox-rx = <0 0 3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 3. /* AM65x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) &cbass_main {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) cbass_main_navss: interconnect0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) mailbox0_cluster0: mailbox@31f80000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) compatible = "ti,am654-mailbox";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) reg = <0x00 0x31f80000 0x00 0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #mbox-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ti,mbox-num-users = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ti,mbox-num-fifos = <16>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) interrupt-parent = <&intr_main_navss>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) interrupts = <164 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ti,mbox-tx = <1 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ti,mbox-rx = <0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
Orange Pi5 kernel
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