Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) MediaTek GCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) ===============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) The Global Command Engine (GCE) is used to help read/write registers with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) critical time limitation, such as updating display configuration during the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) vblank. The GCE can be used to implement the Command Queue (CMDQ) driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) CMDQ driver uses mailbox framework for communication. Please refer to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) mailbox.txt for generic information about mailbox device-tree bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce" or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   "mediatek,mt6779-gce".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - reg: Address range of the GCE unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - interrupts: The interrupt signal from the GCE block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - clock: Clocks according to the common clock binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - clock-names: Must be "gce" to stand for GCE clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - #mbox-cells: Should be 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	<&phandle channel priority>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	phandle: Label name of a gce node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	channel: Channel of mailbox. Be equal to the thread id of GCE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	priority: Priority of GCE thread.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Required properties for a client device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - mboxes: Client use mailbox to communicate with GCE, it should have this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)   property and list of phandle, mailbox specifiers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Optional properties for a client device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - mediatek,gce-client-reg: Specify the sub-system id which is corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)   to the register address, it should have this property and list of phandle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)   sub-system specifiers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)   <&phandle subsys_number start_offset size>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)   phandle: Label name of a gce node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)   subsys_number: specify the sub-system id which is corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)                  to the register address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)   start_offset: the start offset of register address that GCE can access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)   size: the total size of register address that GCE can access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 'dt-binding/gce/mt8183-gce.h' or 'dt-bindings/gce/mt6779-gce.h'. Such as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) sub-system ids, thread priority, event ids.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	gce: gce@10212000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		compatible = "mediatek,mt8173-gce";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		reg = <0 0x10212000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		clocks = <&infracfg CLK_INFRA_GCE>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		clock-names = "gce";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		#mbox-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) Example for a client device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	mmsys: clock-controller@14000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		compatible = "mediatek,mt8173-mmsys";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 			 <&gce 1 CMDQ_THR_PRIO_LOWEST>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		mutex-event-eof = <CMDQ_EVENT_MUTEX0_STREAM_EOF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 				CMDQ_EVENT_MUTEX1_STREAM_EOF>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 					  <&gce SUBSYS_1401XXXX 0x2000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	};