^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Open PIC Binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) This binding specifies what properties must be available in the device tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) representation of an Open PIC compliant interrupt controller. This binding is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) based on the binding defined for Open PIC in [1] and is a superset of that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) binding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) NOTE: Many of these descriptions were paraphrased here from [1] to aid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) readability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - compatible: Specifies the compatibility list for the PIC. The type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) shall be <string> and the value shall include "open-pic".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - reg: Specifies the base physical address(s) and size(s) of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) PIC's addressable register space. The type shall be <prop-encoded-array>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - interrupt-controller: The presence of this property identifies the node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) as an Open PIC. No property value shall be defined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - #interrupt-cells: Specifies the number of cells needed to encode an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) interrupt source. The type shall be a <u32> and the value shall be 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - #address-cells: Specifies the number of cells needed to encode an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) address. The type shall be <u32> and the value shall be 0. As such,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 'interrupt-map' nodes do not have to specify a parent unit address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - pic-no-reset: The presence of this property indicates that the PIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) shall not be reset during runtime initialization. No property value shall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) be defined. The presence of this property also mandates that any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) initialization related to interrupt sources shall be limited to sources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) explicitly referenced in the device tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Interrupt Specifier Definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Interrupt specifiers consists of 2 cells encoded as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - <1st-cell>: The interrupt-number that identifies the interrupt source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - <2nd-cell>: The level-sense information, encoded as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 0 = low-to-high edge triggered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 1 = active low level-sensitive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 2 = active high level-sensitive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 3 = high-to-low edge triggered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Examples
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) Example 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * An Open PIC interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mpic: pic@40000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) // This is an interrupt controller node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) // No address cells so that 'interrupt-map' nodes which reference
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) // this Open PIC node do not need a parent address specifier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #address-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) // Two cells to encode interrupt sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) // Offset address of 0x40000 and size of 0x40000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) reg = <0x40000 0x40000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) // Compatible with Open PIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) compatible = "open-pic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) // The PIC shall not be reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) pic-no-reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) Example 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * An interrupt generating device that is wired to an Open PIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) serial0: serial@4500 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) // Interrupt source '42' that is active high level-sensitive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) // Note that there are only two cells as specified in the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) // parent's '#interrupt-cells' property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) interrupts = <42 2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) // The interrupt controller that this device is wired to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) interrupt-parent = <&mpic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * References
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) [1] Devicetree Specification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) (https://www.devicetree.org/specifications/)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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