Orange Pi5 kernel

Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards

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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) Specifying interrupt information for devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) ============================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 1) Interrupt client nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) -------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) Nodes that describe devices which generate interrupts must contain an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) "interrupts" property, an "interrupts-extended" property, or both. If both are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) present, the latter should take precedence; the former may be provided simply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) for compatibility with software that does not recognize the latter. These
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) properties contain a list of interrupt specifiers, one per output interrupt. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) format of the interrupt specifier is determined by the interrupt controller to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) which the interrupts are routed; see section 2 below for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)   Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	interrupt-parent = <&intc1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	interrupts = <5 0>, <6 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) The "interrupt-parent" property is used to specify the controller to which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) interrupts are routed and contains a single phandle referring to the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) controller node. This property is inherited, so it may be specified in an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) interrupt client node or in any of its parent nodes. Interrupts listed in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) "interrupts" property are always in reference to the node's interrupt parent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) The "interrupts-extended" property is a special form; useful when a node needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) to reference multiple interrupt parents or a different interrupt parent than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) the inherited one. Each entry in this property contains both the parent phandle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) and the interrupt specifier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)   Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 2) Interrupt controller nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) -----------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) A device is marked as an interrupt controller with the "interrupt-controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) property. This is a empty, boolean property. An additional "#interrupt-cells"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) property defines the number of cells needed to specify a single interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) It is the responsibility of the interrupt controller's binding to define the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) length and format of the interrupt specifier. The following two variants are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) commonly used:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)   a) one cell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)   -----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)   The #interrupt-cells property is set to 1 and the single cell defines the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)   index of the interrupt within the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)   Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	vic: intc@10140000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		compatible = "arm,versatile-vic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		reg = <0x10140000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	sic: intc@10003000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		compatible = "arm,versatile-sic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		reg = <0x10003000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		interrupt-parent = <&vic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		interrupts = <31>; /* Cascaded to vic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)   b) two cells
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)   ------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)   The #interrupt-cells property is set to 2 and the first cell defines the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)   index of the interrupt within the controller, while the second cell is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)   to specify any of the following flags:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)     - bits[3:0] trigger type and level flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)         1 = low-to-high edge triggered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)         2 = high-to-low edge triggered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)         4 = active high level-sensitive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)         8 = active low level-sensitive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)   Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	i2c@7000c000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		gpioext: gpio-adnp@41 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			compatible = "ad,gpio-adnp";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			reg = <0x41>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 			interrupt-parent = <&gpio>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 			interrupts = <160 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			#gpio-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 			interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			#interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 			nr-gpios = <64>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		sx8634@2b {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			compatible = "smtc,sx8634";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			reg = <0x2b>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			interrupt-parent = <&gpioext>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			interrupts = <3 0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			threshold = <0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			sensitivity = <7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 3) Interrupt wakeup parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) --------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) Some interrupt controllers in a SoC, are always powered on and have a select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) interrupts routed to them, so that they can wakeup the SoC from suspend. These
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) interrupt controllers do not fall into the category of a parent interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) controller and can be specified by the "wakeup-parent" property and contain a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) single phandle referring to the wakeup capable interrupt controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)    Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	wakeup-parent = <&pdc_intc>;