^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Wondermedia I2C Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - compatible : should be "wm,wm8505-i2c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - reg : Offset and length of the register set for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - interrupts : <IRQ> where IRQ is the interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - clocks : phandle to the I2C clock source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Optional properties :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - clock-frequency : desired I2C bus clock frequency in Hz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Valid values are 100000 and 400000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Default to 100000 if not specified, or invalid value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Example :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) i2c_0: i2c@d8280000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) compatible = "wm,wm8505-i2c";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) reg = <0xd8280000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) interrupts = <19>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) clocks = <&clki2c0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) clock-frequency = <400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };