^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) ST Microelectronics DDC I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible : Must be "st,ddci2c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - reg: physical base address of the controller and length of memory mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - interrupts: interrupt number to the cpu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - Child nodes conforming to i2c bus binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Examples :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)