^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) I2C for SiRFprimaII platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible : Must be "sirf,prima2-i2c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - reg: physical base address of the controller and length of memory mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - interrupts: interrupt number to the cpu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) The absence of the property indicates the default frequency 100 kHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Examples :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) i2c0: i2c@b00e0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) compatible = "sirf,prima2-i2c";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) reg = <0xb00e0000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) interrupts = <24>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };