^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Qualcomm Camera Control Interface (CCI) I2C controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) PROPERTIES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Value type: <string>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Definition: must be one of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) "qcom,msm8916-cci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) "qcom,msm8996-cci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) "qcom,sdm845-cci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Definition: base address CCI I2C controller and length of memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) mapped region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Definition: specifies the CCI I2C interrupt. The format of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) specifier is defined by the binding document describing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) the node's interrupt parent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Definition: a list of phandle, should contain an entry for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) entries in clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Value type: <string>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Definition: a list of clock names, must include "cci" clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - power-domains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) Usage: required for "qcom,msm8996-cci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) Definition:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) SUBNODES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8996 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) sdm845), described as subdevices named "i2c-bus@0" and "i2c-bus@1".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PROPERTIES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) - reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) Value type: <u32>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) Definition: Index of the CCI bus/master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) - clock-frequency:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) Usage: optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) Value type: <u32>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) Definition: Desired I2C bus clock frequency in Hz, defaults to 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) kHz if omitted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) cci@a0c000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) compatible = "qcom,msm8996-cci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) reg = <0xa0c000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) clocks = <&mmcc MMSS_MMAGIC_AHB_CLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) <&mmcc CAMSS_TOP_AHB_CLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) <&mmcc CAMSS_CCI_AHB_CLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) <&mmcc CAMSS_CCI_CLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) <&mmcc CAMSS_AHB_CLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) clock-names = "mmss_mmagic_ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "camss_top_ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "cci_ahb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) "cci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) "camss_ahb";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) i2c-bus@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) clock-frequency = <400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) i2c-bus@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) clock-frequency = <400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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