Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Register-based I2C Bus Mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) This binding describes an I2C bus multiplexer that uses a single register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) to route the I2C signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - compatible: i2c-mux-reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)   port is connected to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Standard I2C mux properties. See i2c-mux.txt in this directory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * I2C child bus nodes. See i2c-mux.txt in this directory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - reg: this pair of <offset size> specifies the register to control the mux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   The <offset size> depends on its parent node. It can be any memory-mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   address. The size must be either 1, 2, or 4 bytes. If reg is omitted, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   resource of this device will be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - little-endian: The existence indicates the register is in little endian.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - big-endian: The existence indicates the register is in big endian.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)   If both little-endian and big-endian are omitted, the endianness of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   CPU will be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - write-only: The existence indicates the register is write-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - idle-state: value to set the muxer to when idle. When no value is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)   given, it defaults to the last value used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Whenever an access is made to a device on a child bus, the value set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) in the relevant node's reg property will be output to the register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) If an idle state is defined, using the idle-state (optional) property,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) whenever an access is not being made to a device on a child bus, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) register will be set according to the idle value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) If an idle state is not defined, the most recently used value will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) left programmed into the register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) Example of a mux on PCIe card, the host is a powerpc SoC (big endian):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	i2c-mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		/* the <offset size> depends on the address translation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		 * of the parent device. If omitted, device resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		 * will be used instead. The size is to determine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		 * whether iowrite32, iowrite16, or iowrite8 will be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		reg = <0x6028 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		little-endian;		/* little endian register on PCIe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		compatible = "i2c-mux-reg";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		i2c-parent = <&i2c1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		i2c@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 			reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 			#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 			si5338: clock-generator@70 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 				compatible = "silabs,si5338";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 				reg = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 				/* other stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		i2c@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 			/* data is written using iowrite32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 			reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 			#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 			#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 			si5338: clock-generator@70 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 				compatible = "silabs,si5338";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 				reg = <0x70>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 				/* other stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	};