^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) General Purpose I2C Bus Mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) This binding describes an I2C bus multiplexer that uses a mux controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) from the mux subsystem to route the I2C signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) .-----. .-----.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) | dev | | dev |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) .------------. '-----' '-----'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) | SoC | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) | | .--------+--------'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) | .------. | .------+ child bus A, on MUX value set to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) | | I2C |-|--| Mux |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) | '------' | '--+---+ child bus B, on MUX value set to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) | .------. | | '----------+--------+--------.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) | | MUX- | | | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) | | Ctrl |-|-----+ .-----. .-----. .-----.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) | '------' | | dev | | dev | | dev |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) '------------' '-----' '-----' '-----'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - compatible: i2c-mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) port is connected to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - mux-controls: The phandle of the mux controller to use for operating the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) mux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Standard I2C mux properties. See i2c-mux.txt in this directory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * I2C child bus nodes. See i2c-mux.txt in this directory. The sub-bus number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) is also the mux-controller state described in ../mux/mux-controller.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - mux-locked: If present, explicitly allow unrelated I2C transactions on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) parent I2C adapter at these times:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) + during setup of the multiplexer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) + between setup of the multiplexer and the child bus I2C transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) + between the child bus I2C transaction and releasing of the multiplexer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) + during releasing of the multiplexer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) However, I2C transactions to devices behind all I2C multiplexers connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) to the same parent adapter that this multiplexer is connected to are blocked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) for the full duration of the complete multiplexed I2C transaction (i.e.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) including the times covered by the above list).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) If mux-locked is not present, the multiplexer is assumed to be parent-locked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) This means that no unrelated I2C transactions are allowed on the parent I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) adapter for the complete multiplexed I2C transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) The properties of mux-locked and parent-locked multiplexers are discussed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) in more detail in Documentation/i2c/i2c-topology.rst.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) For each i2c child node, an I2C child bus will be created. They will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) be numbered based on their order in the device tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) Whenever an access is made to a device on a child bus, the value set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) in the relevant node's reg property will be set as the state in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) mux controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) mux: mux-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) compatible = "gpio-mux";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #mux-control-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) <&pioA 1 GPIO_ACTIVE_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) i2c-mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) compatible = "i2c-mux";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) mux-locked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) i2c-parent = <&i2c1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) mux-controls = <&mux>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) i2c@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ssd1307: oled@3c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) compatible = "solomon,ssd1307fb-i2c";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) reg = <0x3c>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pwms = <&pwm 4 3000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) reset-gpios = <&gpio2 7 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) reset-active-low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) i2c@3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) reg = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) pca9555: pca9555@20 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) compatible = "nxp,pca9555";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) gpio-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #gpio-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) reg = <0x20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
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Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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