^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) MediaTek MT7621/MT7628 I2C master controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - compatible: Should be one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - "mediatek,mt7621-i2c": for MT7621/MT7628/MT7688 platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - #address-cells: should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - #size-cells: should be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - reg: Address and length of the register set for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - resets: phandle to the reset controller asserting this device in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) See ../reset/reset.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Optional properties :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) i2c: i2c@900 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) compatible = "mediatek,mt7621-i2c";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) reg = <0x900 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) resets = <&rstctrl 16>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) reset-names = "i2c";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };