Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * MediaTek's I2C controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) The MediaTek's I2C controller is used to interface with I2C devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)   - compatible: value should be either of the following.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)       "mediatek,mt2701-i2c", "mediatek,mt6577-i2c": for MediaTek MT2701
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)       "mediatek,mt2712-i2c": for MediaTek MT2712
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)       "mediatek,mt6577-i2c": for MediaTek MT6577
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)       "mediatek,mt6589-i2c": for MediaTek MT6589
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)       "mediatek,mt6797-i2c", "mediatek,mt6577-i2c": for MediaTek MT6797
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)       "mediatek,mt7622-i2c": for MediaTek MT7622
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)       "mediatek,mt7623-i2c", "mediatek,mt6577-i2c": for MediaTek MT7623
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)       "mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)       "mediatek,mt8173-i2c": for MediaTek MT8173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)       "mediatek,mt8183-i2c": for MediaTek MT8183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)       "mediatek,mt8192-i2c": for MediaTek MT8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)       "mediatek,mt8516-i2c", "mediatek,mt2712-i2c": for MediaTek MT8516
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)   - reg: physical base address of the controller and dma base, length of memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)     mapped region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   - interrupts: interrupt number to the cpu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)   - clock-div: the fixed value for frequency divider of clock source in i2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)     module. Each IC may be different.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)   - clocks: clock name from clock manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)   - clock-names: Must include "main" and "dma", "arb" is for multi-master that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)     one bus has more than two i2c controllers, if enable have-pmic need include
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)     "pmic" extra.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)   - clock-frequency: Frequency in Hz of the bus when transfer, the default value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)     is 100000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)   - mediatek,have-pmic: platform can control i2c form special pmic side.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)     Only mt6589 and mt8135 support this feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)   - mediatek,use-push-pull: IO config use push-pull mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	i2c0: i2c@1100d000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 			compatible = "mediatek,mt6577-i2c";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 			reg = <0x1100d000 0x70>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 			      <0x11000300 0x80>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 			clock-frequency = <400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 			mediatek,have-pmic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 			clock-div = <16>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 			clocks = <&i2c0_ck>, <&ap_dma_ck>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 			clock-names = "main", "dma";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)