^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) IMG Serial Control Bus (SCB) I2C Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible: "img,scb-i2c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - reg: Physical base address and length of controller registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - interrupts: Interrupt number used by the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - clocks : Should contain a clock specifier for each entry in clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - clock-names : Should contain the following entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) "scb", for the SCB core clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) "sys", for the system clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - clock-frequency: The I2C bus frequency in Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - #address-cells: Should be <1>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - #size-cells: Should be <0>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) i2c@18100000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) compatible = "img,scb-i2c";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) reg = <0x18100000 0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) clocks = <&i2c0_clk>, <&system_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) clock-names = "scb", "sys";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) clock-frequency = <400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };