^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) I2C for Hisilicon hix5hd2 chipset platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible: Must be "hisilicon,hix5hd2-i2c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - reg: physical base address of the controller and length of memory mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - interrupts: interrupt number to the cpu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - clocks: phandles to input clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - Child nodes conforming to i2c bus binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) I2C0@f8b10000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) compatible = "hisilicon,hix5hd2-i2c";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) reg = <0xf8b10000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) interrupts = <0 38 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) clocks = <&clock HIX5HD2_I2C0_RST>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) }