Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Samsung's High Speed I2C controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) The Samsung's High Speed I2C controller is used to interface with I2C devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) at various speeds ranging from 100khz to 3.4Mhz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)   - compatible: value should be.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 	-> "samsung,exynos5-hsi2c", (DEPRECATED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 				for i2c compatible with HSI2C available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 				on Exynos5250 and Exynos5420 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	-> "samsung,exynos5250-hsi2c", for i2c compatible with HSI2C available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 				on Exynos5250 and Exynos5420 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	-> "samsung,exynos5260-hsi2c", for i2c compatible with HSI2C available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 				on Exynos5260 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	-> "samsung,exynos7-hsi2c", for i2c compatible with HSI2C available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 				on Exynos7 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   - reg: physical base address of the controller and length of memory mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)     region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)   - interrupts: interrupt number to the cpu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   - #address-cells: always 1 (for i2c addresses)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)   - #size-cells: always 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)   - Pinctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)     - pinctrl-0: Pin control group to be used for this controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)     - pinctrl-names: Should contain only one value - "default".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)   - clock-frequency: Desired operating frequency in Hz of the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)     -> If not specified, the bus operates in fast-speed mode at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)        at 100khz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)     -> If specified, the bus operates in high-speed mode only if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)        clock-frequency is >= 1Mhz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) hsi2c@12ca0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	compatible = "samsung,exynos5250-hsi2c";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	reg = <0x12ca0000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	interrupts = <56>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	clock-frequency = <100000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	pinctrl-0 = <&i2c4_bus>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	s2mps11_pmic@66 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		compatible = "samsung,s2mps11-pmic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		reg = <0x66>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };