Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) I2C for Atmel platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible : Must be one of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 	"atmel,at91rm9200-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 	"atmel,at91sam9261-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	"atmel,at91sam9260-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 	"atmel,at91sam9g20-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 	"atmel,at91sam9g10-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	"atmel,at91sam9x5-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	"atmel,sama5d4-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	"atmel,sama5d2-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	"microchip,sam9x60-i2c".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - reg: physical base address of the controller and length of memory mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)      region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - interrupts: interrupt number to the cpu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - clocks: phandles to input clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - dmas: A list of two dma specifiers, one for each entry in dma-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - dma-names: should contain "tx" and "rx".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)   capable I2C controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - i2c-sda-hold-time-ns: TWD hold time, only available for:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	"atmel,sama5d4-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	"atmel,sama5d2-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	"microchip,sam9x60-i2c".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - scl-gpios: specify the gpio related to SCL pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - sda-gpios: specify the gpio related to SDA pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - pinctrl: add extra pinctrl to configure i2c pins to gpio function for i2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)   bus recovery, call it "gpio" state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - Child nodes conforming to i2c bus binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) Examples :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) i2c0: i2c@fff84000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	compatible = "atmel,at91sam9g20-i2c";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	reg = <0xfff84000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	interrupts = <12 4 6>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	clocks = <&twi0_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	clock-frequency = <400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	24c512@50 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		compatible = "atmel,24c512";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		reg = <0x50>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		pagesize = <128>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) i2c0: i2c@f8034600 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	compatible = "atmel,sama5d2-i2c";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	reg = <0xf8034600 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	dmas = <&dma0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		AT91_XDMAC_DT_PERID(11)>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	       <&dma0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		AT91_XDMAC_DT_PERID(12)>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	dma-names = "tx", "rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	clocks = <&flx0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	atmel,fifo-size = <16>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	i2c-sda-hold-time-ns = <336>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	pinctrl-names = "default", "gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	pinctrl-0 = <&pinctrl_i2c0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	pinctrl-1 = <&pinctrl_i2c0_gpio>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	wm8731: wm8731@1a {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 		compatible = "wm8731";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 		reg = <0x1a>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };