Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Device tree configuration for the I2C busses on the AST24XX, AST25XX, and AST26XX SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - #address-cells	: should be 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - #size-cells		: should be 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - reg			: address offset and range of bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - compatible		: should be "aspeed,ast2400-i2c-bus"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 			  or "aspeed,ast2500-i2c-bus"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 			  or "aspeed,ast2600-i2c-bus"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - clocks		: root clock of bus, should reference the APB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 			  clock in the second cell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - resets		: phandle to reset controller with the reset number in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 			  the second cell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - interrupts		: interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Optional Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - bus-frequency	: frequency of the bus clock in Hz defaults to 100 kHz when not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		  specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - multi-master	: states that there is another master active on this bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) i2c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	compatible = "simple-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	ranges = <0 0x1e78a000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	i2c_ic: interrupt-controller@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		compatible = "aspeed,ast2400-i2c-ic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		reg = <0x0 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		interrupts = <12>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	i2c0: i2c-bus@40 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		#interrupt-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		reg = <0x40 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		compatible = "aspeed,ast2400-i2c-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		clocks = <&syscon ASPEED_CLK_APB>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		resets = <&syscon ASPEED_RESET_I2C>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		bus-frequency = <100000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		interrupts = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		interrupt-parent = <&i2c_ic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };